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dsPICDEM? MC1 Motor Control Development Board
1.4
PORT ALLOCATIONS
The following table shows the primary port allocations for the dsPIC30F6010 as required
for interfacing to one of the custom power modules via J1. Where a primary assignment
and use is not shown, the pin is available on one of the prototyping headers.
The pin headers give access to all pins. In addition, certain other pins are routed to the
analog (J6) and digital (J7) prototyping headers.
Pin No.
23
25
52
53
20
19
18
17
16
15
21
22
27
28
29
30
33
34
35
36
Port
A
A
A
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
Port No.
9
10
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pri
Assignment
RA9
RA10
RA14
RA15
AN0
AN1
AN2
INDX
QEA
QEB
AN6
—
AN8
AN9
AN10
AN11
AN12
AN13
AN14
OCFB
Pri Use
LED1 (D6)
LED2 (D7)
LED3 (D8)
LED4 (D9)
PHASE#1_I_F/B via J1
PHASE#2_I_F/B via J1
PHASE#3_I_F/B via J1
INDEX for QEI via J5 (Z)
QEI Channel A via J5 (A)
QEI Channel B via J5 (B)
PFC HALL via J1
—
BUS_SHUNT via J1
? VAC ? _SENSE
PHASE#4_SHUNT
VLINK_SENSE
VPH_#1
VPH_#2
VPH_#3
Active Low FAULT from power
Suggested Alternative Use
V REF - via J6 (RA9) (D6–NF)
V REF + via J6 (R10) (D7–NF)
—
—
ICSP? Data if S2 in PRI Position
ICSP Clock is S2 in PRI Position
ADC input via J6 (AN2) (LK3-NF)
ADC input via J6 (AN3) or Pin5 J5
ADC input via J6 (AN4) or Pin3 J5
ADC input via J6 (AN5) or Pin4 J5
ADC input via J6 (AN6)
AN7/RB7 via J6 (AN7)
ADC input via J6 (AN8)
ADC input via J6 (AN9)
ADC input via J6 (AN10)
ADC input via J6 (AN11)
ADC input via J6 (AN12)
ADC input via J6 (AN13)
ADC input via J6 (AN14)
—
module of TRIP switch
4
5
59
60
58
61
62
63
66
67
68
69
C
C
C
C
D
D
D
D
D
D
D
D
1
3
13
14
0
1
2
3
4
5
6
7
RC1
RC3
—
—
RD0
RD1
RD2
RD3
OC5
OC6
—
UPDN
LCD R/W Line
LCD RS Line
ICSP Data if S2 in ALT Position
ICSP Clock if S2 in ALT Position
LCD0 (LSB)
LCD1
LCD2
LCD3 (MSB)
BRAKE_FIRE via J1
PFC_FIRE via J1
—
QEI UP/DOWN Output to
—
—
—
—
—
—
—
—
—
—
OC7/CN15/RD6 via J7 (RD6)
RD7 output to Direction LED (D5)
Direction LED (D5)
54
D
8
IC1
Phase A Position Hall via J3 (A)
Back EMF Crossing #1 via J1 if
LK4 in Position 2-3
55
D
9
IC2
Phase B Position Hall via J3 (B)
Back EMF Crossing #2 via J1 if
LK5 in Position 2-3
56
57
64
65
D
D
D
D
10
11
12
13
IC3
RD11
—
RD13
Phase C Position Hall via J3 (B)
Active Low FIRE_ENABLE
—
LCDENA
Back EMF Crossing #3 via J1
—
IC5/RD12 via J7 (RD12)
—
DS70098A-page 12
? 2003 Microchip Technology Inc.
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